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Power Supply Controller for Portable Pentium (R) II & III SpeedStep Processors
POWER MANAGEMENT Description
The SC1406G PowerStep controller is a High Speed, High Performance Hysteretic Mode PWM controller. Teamed with the SC1405 Smart Driver, it powers advanced Pentium(R) II and Pentium(R) III processors. The SC1406G features Intel Mobile Voltage Positioning (IMVP), which increases battery life by reducing the voltage at the processor when it is heavily loaded. It also directly supports Intels SpeedStep processors for even longer battery life. A 5-bit DAC, accurate to 0.85%, sets the output voltage reference, and implements the 0.925V to 2.00V range of the mobile Pentium(R) specifications. The hysteretic converter uses a comparator without an error amplifier, and therefore provides the fastest possible transient response, while avoiding the stability issues inherent to classical PWM controllers. Two linear regulator controllers, coupled with appropriate external transistors, produce tightly regulated 1.5V and 2.5V to complete the processor power solution. The SC1406G also features separate soft-start controls for the converter and the regulators, a TTLcompatible power good indication, logic enable, and low battery undervoltage lockout. Programmable current limiting uses a separate comparator to protect against overloads and short-circuits.
SC1406G
Features
u High-speed hysteretic controller provides high effi u u u u
ciency over a wide operating load range Inherently stable Complete CPU power solution with two LDO drivers Programmable core voltage for Pentium(R) II & III pro cessors Native Speed Step(R) support
Applications
u Laptop and notebook computers u High performance microprocessor-based systems u High efficiency distributed power supplies
Conceptual Application Circuit
+V_5
+V_IN
PWM Controller
SC1405 SC1405
Smart Smart MOSFET MOSFET Driver Driver
Lo
+VCC_CPU_CORE +VCC_CPU_CORE Co
0.925V-2.0V Up to 14A
IMVP IMVP CONTROLLER CONTROLLER
SC1406G SC1406G
3.3V
1.5V 2.5A +VCC_CPU_IO +VCC_CPU_IO
VID [4:0] VID [4:0]
LDO Controller 3.3V 2.5V 150mA +VCC_CPU_CLK +VCC_CPU_CLK LDO Controller
Revision 8/3/2000
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SC1406G
POWER MANAGEMENT Absolute Maximum Rating
PAR AMETER VC C Supply Voltage Low Battery Input Enable All other I/O pi ns Operati ng Juncti on Temperature Lead Temperature (Solderi ng 10 seconds) Storage Temperature TJ TL TSTG LBIN EN SYMB OL MAXIMU M -0.3 to 7 -0.3 to 7 -0.3 to 7 GND - 0.3 to VC C + 0.3 0 to +125 300 -65 to 150 U N ITS V V V V C C C
Electrical Characteristics
PA R A M E T E R Su p p l y ( V CC) Inp ut Sup p ly Voltage Range Quiescent Current ICCQ SYM B OL
Unless specified: -0 < TA < 100C; VCC = 3.3V (See test circuit)
CO N DI T I O N S MIN T YP MA X U N IT S
3.0 EN is low, 3.0V < V CC < 3.6V EN is h igh and th e LBIN is in UV LO
3.3
6.0 10 350
V A
Op erating Current Und er Voltage Lock Out Th resh old Und er Voltage Lock Out Hy steresis E n ab l e I n p u t Inp ut High Inp ut Low L o w B at t e r y M o n i t o r ( L B I N ) UV LO Th resh old Inp ut Bias Current
ICC
E N i s h i gh 2.7 20
4
15 2.95
mA V mV
3.0 < V CC < 5V
0.7*V CC 0.8
V V
V THDC
V LBIN > V THDC > V THDC V LBIN < V THDC
1.175
1.225
1.275 0.3
V A
0.6
1.0
10.5
V CORE Pow er Good Generator: (N ote th at d uring th e 50 s latency time of any V ID cod e ch ange, th e PWRGD outp ut signal may ch ange state one or more times). Over-Voltage Th resh old Und er-Voltage Th resh old Outp ut Voltage, High Outp ut Voltage, Low V HCORE V LCORE IPWRGD = 10 A (source) EN is h igh IPWRGD = 10 A (sink), EN is h igh IPWRGD = 10 A (sink), th e b attery is in U V LO V DAC = 0.9V to 1.675V 1.08*V DAC 0.88*V DAC 0.95*V CC 0.4 0.8 1.12*V DAC 0.92*V DAC V V V V V
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SC1406G
POWER MANAGEMENT Electrical Characteristics Continued
PARAMETER SYMBOL
Unless specified: -0 < TA < 100C; VCC = 3.3V (See test circuit)
CON DITION S M IN T YP MA X U N IT S
Core Conver ter Soft Star t Current Core Conver ter Soft-Star t Current ISSCORE Charge (Source) current Discharge (Sink) current VSSCORE Soft-Star t Termination VSSCORE Discharge Threshold VID DAC VID Inp ut High Threshold VID Inp ut Low Threshold VID Inp ut Pull-Up Current,VID (0-4) Outp ut Voltage Accuracy Settling Time* VID (0-4) = 00000...11111 IDAC = 0, VID(0-4) = 00000...11111 CDAC = 1000p F VID is set to change VCORE from CORE Comp arator (CMP, CMPREF, HYS, CO) Inp ut Bias Current Inp ut Offset Voltage Hysteresis Setting Current ICMPREF V CMP = VCMPREF = 1.3V V CMPREF = 1.3V RHYS = op en RHYS = 170kW RHYS = 17kW Outp ut Voltage High Outp ut Voltage Low Prop agation Delay Time** Measured at device p ins, from the trip p oint to 50% of CO transition. Outp ut Rise/Fall Times** Measured b etw een 30% and 70% p oints of CO transition TR Load Imp edance = 100k in p arallel w ith 10p F, VCC = 3.0V Load Imp edance = 100k in p arallel w ith 10p F, VCC = 3.6V V CMPREF = 1.3V, D VCMP = 40mV (20mV overdrive) TA = 25C TA = full range CCO = 10p F VCC = 3.0V RCO = 100K 7 7 85 2.5 0.4 20 30 10 100 1.5 2 3 2 13 115 V V ns A A mV 6 -0.85 3.0V < VCC < 3.6V 0.7*Vc 0.8 40 +0.85 35 A % s V 0.6 0.30 1.90 1 1 2.00 150 2.10 400 1.45 A mA V mV
10
ns
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SC1406G
POWER MANAGEMENT Electrical Characteristics Continued
PARAMETER SYMBOL
Unless specified: -0 < TA < 100C; VCC = 3.3V (See test circuit)
CON DITION S M IN T YP MA X U N IT S
Current Limit Comp arator (CL, CLREF, CLSET) Inp ut Bias Current Current Limit Setting Current |ICLREF| V CL = 1.3V RCLSET = op en V CLREF VCL = 10mV VCLREF VCL = -10mV RCLSET = 170kW VCLREF VCL = 10mV V CLREF VCL = -10mV RCLSET = 42.5kW VCLREF VCL = 10mV V CLREF VCL = -10mV RCLSET = 20kW VCLREF VCL = 10mV V CLREF VCL = -10mV RCLSET = 17kW VCLREF VCL = 10mV V CLREF VCL = -10mV Inp ut Offset Voltage Prop agation Delay Time** Measured at the device p ins, from the trip p oint to 50% of CO transition V CL - VCLREF VCLREF = 1.3V V CLREF = 1.3V, D VCMP = 50mV (20mV overdrive) TA = 25C 19.5 30 5 7.5 A A
5.0
40.5 A
13
20
27
100.5
120
139.5 A
67
80
93
222
255
288 A
148
170
192
262.5
300
337.5 A
175
200
225
4
6 100 150
mV ns
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SC1406G
POWER MANAGEMENT Electrical Characteristics Continued
PARAMETER SYMBOL
Unless specified: -0 < TA < 100C; VCC = 3.3V (See test circuit)
CON DITION S 1.5V Linear Regulator Controller M IN T YP MA X U N IT S
Inp ut Bias Current Outp ut Voltage, V FB15 CO_1.5 = 56F, 20mW ESR max or 150F, 45mW ESR max Cap acitance tolerance = 20% Base Drive Outp ut Current
V FB15 = 1.5V External p np BJT w ith BMIN > 50 @ IC = 500mA IO = 0mA to 500mA TA = 25C 2.5V Linear Regulator Controller 1.47 1.50
1 1.54
mA V
10
120
mA
Inp ut Bias Current Outp ut Voltage, V FB15 CO_1.5 = 56F, 20mW ESR max or 150F, 45mW ESR max Cap acitance tolerance = 20% Base Drive Outp ut Current
V FB15 = 2.5V External p np BJT w ith BMIN > 50 @ IC = 100mA IO = 0mA to 100mA TA = 25C Linear Regulator Soft Star t (LRSS) 2.45 2.50
1 2.55
mA V
2.5
20
mA
Linear Reg Soft Star t Current
ILRSS
Charge Current = VLRSS = 0V Discharge Current, V LRSS = 1.50V, EN is low or the b attery is in UVLO
-0.6 0.3 150 1.53
-1 1
-1.45
A mA
Enab le Threshold Soft-Star t Termination Threshold
400 1.87
mA V
1.70
Voltage Clamp (VCIN , VCOUT, VCBYP) (N ote: This circuit section is rarely used). Inp ut Voltage Outp ut Voltage RVCOUT = 150W tied to V S = 2.5V IVCIN = -10A VCIN is Op en VVCIN = 0.175V 0.93 0.8Vs 1.5 1.60 Vs 0.375 10 nS V V
Progagation Delay**
RVCOUT = 150W tied to VS = 2.5V CVCBYP = 1500p F, VCIN step s from 0.175V to 1.50V and b ack. Measured from 50% of VCIN step to 50% of VCOUT transient
* Guaranteed by design. **Guaranteed by characterization.
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SC1406G
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
DEV ICE SC1406GCTSTR PA CKA GE TSSOP-28 TEMP. (TJ) 0 to 125C
Note: Only available in tape and reel packaging. A reel contains 2500 devices.
TSSOP - 28
Block Diagram
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SC1406G
POWER MANAGEMENT Pin Descriptions
Pi n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin N ame HYS CLSET V COUT V CIN V CBYP V ID4 V ID3 V ID2 V ID1 V ID0 BA SE 25 FB25 BA SE 15 FB15 EN PWRGD Pin Function Core comp arator h y steresis setting. Current limit setting. Voltage clamp outp ut. Leave op en if not used . Voltage clamp inp ut. Tie to GN D if not used . Voltage clamp b y p ass p in. Req uires a 1500p F cap from th is p in to GN D. Leave op en if not used . V ID (voltage id entification) most significant b it. V ID i n p u t V ID i n p u t V ID i n p u t V ID least significant b it. 2.5V Linear regulator d rive. 2.5V Linear regulator outp ut feed b ack. 1.5V Linear regulator d rive. 1.5V Linear regulator outp ut feed b ack. Enab le. SC1406G is enab led w h en th is logic signal is High . Teamed w ith th e SC1405 d river, th is p in can b e connected to th e PWRDY p in of th e SC1405. Pow er Good . Wh en th e main conver ter outp ut ap p roach es and stay s w ith in 10% of th e V ID DA C setting, and b oth soft-star t p eriod s terminate, th is signal is p ulled up to V CC. During und er-voltage lockout, th is signal is und efined . During a Sp eed Step transition, PWRGD may toggle one or more times. Low b attery inp ut. Th is p in is used to set th e minimum voltage to th e conver ter th rough an external resistor d ivid er. Wh en th e inp ut to th is p in is less th an 1.225V th e SC1406G is h eld in UV LO regard less of th e status of EN . Linear regulators soft star t. During a normal p ow er-up th e external soft-star t cap acitor (1200p F, ty p ) is ch arged b y an internal 1 A current source to set th e ramp -up time of th e linear regulator outp uts, 1.5V and 2.5V. Th is ramp -up time is ty p ically 2ms, 6ms max. Th e cap acitor is d isch arged th rough an internal sw itch w h en EN is low or th e V CC or LBIN p ins are und er voltage. A new soft-star t cy cle w ill not b egin until th e p in voltage d rop s b elow a th resh old of 150mV ty p ical (200mV max). (Th e linear regulator soft-star t current and th e core soft-star t current track each oth er to w ith in 10%.) Main controller CORE outp ut soft star t. During a normal p ow er-up th e external soft-star t cap acitor (1800p F, ty p ) is ch arged b y an internal 1 A current source to set th e ramp -up time of th e linear regulator outp uts, 1.5V and 2.5V. Th is ramp -up time is ty p ically 3ms, 6ms max. Th e cap acitor is d isch arged th rough an internal sw itch w h en EN is low or th e V CC or LBIN p ins are und er voltage. A new soft-star t cy cle w ill not b egin until th e p in voltage d rop s b elow a th resh old of 150mV ty p ical (200mV max). (Th e linear regulator soft-star t current and th e core soft-star t current track each oth er to w ith in 10%.) Main CORE conver ter outp ut feed b ack. Main controller d igital to analog outp ut. Ground Comp arator outp ut. Main regulator controller outp ut used to d rive th e inp ut of th e MOSFET d river IC, such as th e SC1405. Sup p ly voltage inp ut. Th is inp ut is cap ab le of accep ting 3.3V or 5.0V sup p ly voltage. Core comp arator inp ut. Core comp arator reference inp ut. Current limit inp ut. Current limit reference inp ut.
17 18
L B IN SSLR
19
SSCORE
20 21 22 23 24 25 26 27 28
CORE DA C GN D CO V CC CMP CMPREF CL CLREF
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SC1406G
POWER MANAGEMENT VID vs. VDAC Voltage
V ID4 0 0 0 V ID3 0 0 0 V ID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 V ID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 V ID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V DAC (volts) 2.00 1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 N O CPU* 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 N O CPU*
PIN Descriptions
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
* output is disabled
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SC1406G
POWER MANAGEMENT Functional Description
SUPPLY The chip is optimized to operate from a 3.3V + 5% rail but is also designed to work up to 6V maximum supply voltage. UNDER VOLTAGE LOCK-OUT CIRCUIT The under voltage lockout (UVLO) circuit consists of two comparators, the low battery and low VCC (low supply voltage) comparators. The output of the comparator, gated with the Enable signal, turns on or off the internal bias, enables or disables the CO output, and initiates or resets the soft start timers. POWER GOOD GENERATOR If the chip is enabled but not in UVLO condition, and the core voltage gets within +10% of the VID programmed value, then a high level Power Good signal is generated on the PWRGD pin to trigger the CPU power up sequence. If the chip is either disabled or enabled in UVLO condition, then PWRGD stays low. This condition is satisfied by the presence of an internal 200kW pulldown resistor connected from PWRGD to ground. During soft start, PWRGD stays low independently from the status of Vcore voltage. PWRGD is high when all of the following conditions are true: 1 EN is high 2 Soft-start has completed 3 LBIN and VCC are above their under-voltage trip levels. BAND GAP REFERENCE A better than +1% precision band-gap reference acts as the internal reference voltage standard of the chip, which all critical biasing voltages and currents are derived from. All references to VREF in the equations to follow will assume VREF = 1.7V. CORE CONVERTER CONTROLLER Precision VID DAC Reference The 5-bit digital to analog converter (DAC) serves as the programmable reference source of the core comparator. Programming is accomplished by CMOS logic level VID code applied to the DAC inputs. The VID code vs. the DAC output is shown in the Output Voltage Table. The accuracy of the VID DAC is maintained on the same level as the band gap reference. There is a 10A pull-up current on each DAC input when EN is high. Core Comparator This is an ultra-fast hysteretic comparator with a typical propagation delay of approximately 20ns at a 20mV overdrive. This chip can be used in a standard hysteretic mode controller configuration and in an IMVP hysteretic controller scheme. Detailed instructions for the IMVP solution are found in the PowerStep solution design procedure section of this datasheet.
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Current Limit Comparator The current limit comparator monitors the core converter output current and turns the high side switch off when the current exceeds the upper current limit threshold, VHCL and re-enable only if the load current drops below the lower current limit threshold, VLCL. The current is sensed by monitoring the voltage drop across the current sense resistor, RCS, connected in series with the core converter main inductor (the same resistor used for IMVP input signal generation). The thresholds have the following relationships:
VHCL = 3 * VLCL = 2 * VHYSCL =
R CLOH *V REF R CLSET R CLOH *V REF R CLSET
R CLOH *V REF R CLSET
Core Converter Soft Start Timer This circuit controls the ramp-up time of the core voltage in order to reduce the initial inrush current on the core input voltage (battery) rail. The soft-start circuit consists of an internal current source, external soft-start timing capacitor, internal discharge switch across the capacitor, and a comparator monitoring the capacitor voltage. LINEAR REGULATOR CONTROLLERS 1.5V Linear Regulator This block is a low drop-out (LDO) linear-regulator controller, which drives an external PNP bipolar transistor as a pass element. The linear regulator is capable of delivering 500mA steady-state DC current and can support transient currents of greater than 1A, depending on pass element and output capacitor selection. 2.5V Linear Regulator This block is a low drop-out (LDO) linear regulator controller, which drives an external PNP bipolar transistor as a pass element. The LDO linear regulator is capable of delivering 100mA steady-state DC current and can support transient currents greater than 200mA, depending on pass element and output capacitor selection. Linear Regulator Soft-Start The soft-start circuit of the linear regulators is similar to that of the core converter, and is used to control the ramp-up time of the linear regulator output voltages. For maximum flexibility in controlling the start-up sequence, the soft-start function of the linear regulators is separated from that of the core converter.
SC1406G
POWER MANAGEMENT
VOLTAGE CLAMP This level translator converts an input voltage swing on the IO rail, into a voltage swing on the CL or VCC rail depending on where the open-drain output of the translator is tied to through an external pull-up resistor. The level translator tracks the input in phase, and switches in 5ns (typical) following an input threshold intercept.
Gerber Evaluation Board Bill of Materials Applications Information Plots
Power on/off Sequence
PowerStep Solution Design Procedure
Introduction: The SC1406G (PowerStep for SpeedStep) and SC1405 Smart Driver power chip set provides a flexible, high performance power solution to the requirements of Intel(R) mobile SpeedStep processors. The SC1406G is a control IC that integrates a synchronous step-down controller for VCORE and two low-dropout regulator (LDO) controllers for VI/O, and VCLK. In addition, the SC1406G also has a low-battery detector and a clamp circuit. The SC1405 is a Smart Driver IC with programmable dead time and industry-leading speed. The synchronous step-down converter is a hysteretic type, where the output voltage is compared against a VID programmable reference (VDAC) with a resistor programmable offset, VHYS. The basic operation of the converter is very simple: Referring to Figure 1, with the voltage at the reference, QH is off, QL is on and the output filter (L and C) discharge into load R. When the output voltage hits the lower hysteresis point, the switches reverse state, and the RLC network charges up to the upper hysteresis value.
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10
1uF/0805
2
C4
1
CLSET
8 7 6 5
VID4
CO GND 22 R21 1.40k C31 1pF 23
6
VID4
CO 107k
OFFSET
10.0k C14 2 7 0 pF 1
R14
R13
3 2 1
1
VID2
DAC CORE C10 OVPS 1 OVPS EN GND CO SMOD DELAYC PRDY VCC 8 0 C16 C15 47pF 1uF/0805 IRF7811A BG 9 BG PGND 10 2 7 / 1 2 06 R 1 1 B G 14 DSPSDR 11 R17 1nF/0805 DRN 12 TG 13 TG BST 14 C17 0.22uF/0805 2 C11 SSLR 1.2nF 4 5 16 20k 7 EN 15 C12 1nF 43k DELAYC 6 R8 LBIN PWRGD 17 LBIN R9 18 SSLR 3 BST SSCORE 19 SSCORE 1.8nF 1nF 20 C9 21
8
VID2
L1
2
VID1 S C 1 4 05C
9
VID1
CS 1.5uH
C25
2
8 7 6 5
150u/4V
M M B T4403
C18
Q4
D
8 7 6 5
3
3
Q2
IRF7811A 4
1B A S E 151 3
C26
BASE15
2
4
1uF
3 2 1
C27 BG2 R12 0
150uF/4V
2_5V
1_5V
C29 10uF/1206
V_GATE
EN
C13 1nF
3 2 1
1
11
VID0
L R F 3 W _ 0 03_5% C19 150uF/4V Q5
D
10
VID0
4
U2
PHASE
L_R
3
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+3.3V
R19
+5Vcc +V_IN
D1 M B R 0 5 30 C3 4.7uF/50V C2 4.7uF/50V C1 4.7uF/50V
R18 V c c _ 1 4 06
0/0805
U1
R 3 1.00k CLREF 100pF R 4 1.00k CL Q3
D
R1 28 CS+ 27 26 IRF7811A TG1 4 R 6 1.00k R22 C28 100pF CMP C8 VCC 0.22uF/0805 24 25 CMP C7 CMPREF 100pF C6 R5 1 . 0 0 k CORE CL C5 CLREF
127k
HYS CLOH BAL
CS-
GND
HYS
1
HYS
POWER MANAGEMENT Typical Application Schematic
CLSET
C L S ET
2
R2 CMPREF
86.6k
3
VCOUT
4
VCIN
S C 1 4 06G
OH
1uF/50V/1206
5
VCBYP
R15 6.65k R23
VID3
DAC
DAC
7
VID3
+VccCPU_CORE
Q1 1
C21 150uF/4V C20 150uF/4V C22 150uF/4V
C23 NO-POP C24 NO-POP
B A S E25 1 1
BASE25
12
FB25
D2 M B R S 3 40
MJD45H11
14
FB15
SC1406G
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SC1406G
POWER MANAGEMENT
Figure 1 - Hysteretic Converter Basics The major advantages of this approach are simplicity, inherent stability (there are no reactive elements in the control circuit to provide the phase shift required for classical stability problems), and the fastest possible transient response. Any transient which takes the voltage out of the hysteretic range forces the converter immediately into the proper response. There are no error voltages to slew, and no maximum or minimum duty cycle limits to slow the transient response as in most other control schemes. A significant benefit of the controller/driver architecture is that low-level analog control functions do not have to coexist in an environment of thousands of volts and amps per microsecond, reducing noise problems. The SC1406G also supports the Intel Mobile Voltage Positioning (IMVP) functions. In short, IMVP allows notebook designers to reduce the output voltage with increasing load current. This has two potential benefits:
DAC R23 (RCS) +
IOUT
VOUT
+ R6 (ROH) -
+ R5 (RCORE) -
+
CMP (pin 25) CMPREF (pin 26)
+ R22 (ROFFSET) -
R21 (RDAC) +
*
*
IMVP minimizes power by reducing the voltage under heavy loads; processor power is proportional to V2, so a 5% reduction in voltage results in a nearly 10% reduction in power drawn by the processor. IMVP can reduce the number of capacitors required to respond to transients by producing a larger allowable transient; briefly, the no-load voltage is positioned above nominal, so when a transient occurs, the load has farther to drop before hitting the regulation limit. The loaded voltage is allowed to remain below the nominal so that when the load returns to zero, the voltage can rise farther without reaching the transient specification. Since the allowable transient voltages are larger, less capacitance and higher ESR can provide the required performance.
DAC (pin 21)
Figure 2IMVP Example Illustration The SC1406G implements IMVP, previously named DSPS (dynamic set-point switching) in the following manner: Please see Figure 2 above, and assume, for simplicity: * ROFFSET is open * The current into the CMP and CMPREF pins is zero. Then, please note: * The SC1406G regulates to the + side of the current sense resistor, because that is where the CMP pin is tied, and, * No current flows through ROH, since the input current of the comparator is ~0; V(ROH) = 0. * The difference in voltage between CMP and CMPREF is ~0V in order for the controller to be in regulation In these conditions: * At zero load, VOUT = VDAC and the voltage across the current sense resistor is also zero; * As the load increases, a voltage is developed across
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The SC1406G provides the precise voltage positioning required by IMVP because it employs a current-sense resistor, multiplied by a gain set by external resistors to very accurately set the voltage as a function of load current.
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SC1406G
POWER MANAGEMENT
* * * * * * * RCS; V(RCS) = IOUT * RCS. In order to keep the voltage between CMP and CMPREF = 0V, V(RCS) appears across RCORE. V(RCS) + V(RCORE) = 0, so V(RCORE) = -V(RCS); therefore, a current flows through RCORE from VOUT to CMPREF. I(RCORE) = IOUT * RCS / RCORE An equal, but opposite current must flow in RDAC, so the voltage at CMPREF is reduced by I(RCORE) l RDAC, so VCMPREF = VDAC - I(RCORE) * RDAC Substituting the equations from above: VCMPREF = VDAC IOUT * RCS * RDAC / RCORE Since VOUT = VCMPREF V(RCS), with a little algebra: VOUT = VDAC - IOUT * RCS (1 + RDAC / RCORE) in having a larger transient response band to work with, thereby providing a solution with the fewest output capacitors. On the other hand, this also means that at low currents, the processor will burn more power than without the offset, since CV2F still applies, so battery life will be reduced. The numbers in the sample calculations are taken from the Intel Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet, Revision 1.0, Document Number: 245302-002. Please consult the data for your specific processor. Hysteretic Converter Design Equations: The Typical Application Schematic on Page 12 is a schematic of the sample converter. Note that several of the resistors have annotations along with reference designators and values. These resistors set the basic functions and IMVP. Referring to Figure 1, the basic equations for a hysteretic converter are: ( VIN - VOUT) (ESR + RCS) 1) VHYS := d FS L where, 2)
d := TON V OUT VIN
So, with the SC1406G, you get an accurate, linear droop greater than the drop across the current sense resistor, without the efficiency penalty of a large RCS, with a gain that is set by 1% resistors! Adding ROFFSET shifts the position at zero current, as described later. For further information on IMVP, consult the Intel yellow-cover document Intel(R) Mobile Voltage Positioning Voltage Regulation Controller Application Note, Reference Number OR-2101. The SC1405, a smart MOSFET driver, provides industry-leading performance, driving a 3000pF load in under 15nS, typically. Not only does the SC1405 offer built-in shoot-through protection, but also has externally programmable dead time. In addition, it provides other protection and performance features, such as under-voltage lock-out (UVLO), programmable adaptive over-voltage protection (OVP), and the SMOD pin, which may be used to force the low-side gate drive LO during very light load conditions to prevent negative circulating current in the inductor. It comes in the small TSSOP-14 package. DESIGN PROCEDURE: Requirements: The first step in designing any converter is in defining the requirements, which can come from many sources. For the SC1406G, you need to determine the minimum and maximum input voltages, which are determined by the battery and AC adapter characteristics, unless you plan to use an existing regulated voltage, such as +5V. The processor determines other requirements; they are: * * * * * * Maximum output voltage Minimum output voltage Maximum output current Minimum output current Maximum transient current Transient voltage requirements
(TON + TOFF)
d :=
IIn equation 2), d is commonly referred to as the duty cycle. The output voltage of the SC1406G is set digitally by the VID (0:4) inputs, producing a voltage at the DAC output (pin 21) accurate to better than 0.85%. The DAC voltage requirements are given in the referenced Intel document and the SC1406G datasheet. A similarly accurate fixed voltage internal bandgap reference, Vref, has a nominal value of 1.70V, and is used for setting voltage hysteresis and current limiting levels. In addition, these references are used to provide active voltage positioning adjusting the output voltage as a function of load current scaled by external resistors. The output voltage of an IMVP converter has three components: * The programmed DAC voltage, VDAC * The load dependent droop VIMVP * An optional positive offset, VOFFSET In equation form, 3) VOUT := VDAC - VIMVP + VOFFSET The full equations for the IMVP converter are: 4) VOUT :=
13
VDAC ROFFSET + ROH RCORE - IOUT RCS ROFFSET RCORE + RDAC RCORE ROFFSET + RDAC ROH
One decision you need to make is whether a positive offset voltage at zero current is desirable. Providing this offset results
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SC1406G
POWER MANAGEMENT
5)
VRIPPLE := 2 VHYS RCORE ROFFSET + ROH
(
)
RCORE ROFFSET + RDAC ROH
ESR +
RCORE ROFFSET + ROH
(
ESR
)
8)
RCS
ROH + ROFF :=
VNL RDAC VDAC -1
RCORE ROFFSET + RDAC ROH
V NL V DAC
For customers familiar with the Intel IMVP application notes, the above schematic has the IMVP resistors denoted using bold lettering. To these resistors, Semtech has added one additional resistor, RBAL, which is used to balance the impedance at the current limit comparator for improved noise performance. A cross-reference between the IMVP nomenclature and the reference designator in the schematic above is provided in the table below.
Intel Nomenclature RHSY RCLSET RCORE ROH RCLOH RDAC ROFFSET RCS Schematic Reference Designator R1 R2 R5 R6 R3 R21 R22 R23
To disable the no-load positive offset, leave R22 unpopulated. Negative offsets are also possible contact Semtech Applications Engineering for details. The current sense resistor, RCS (R23), RDAC resistor (R21), and RCORE (R5) set the IMVP gain. VIMVP is a function of current, and is subtracted from the zero current output voltage. 9) VIMVP := IOUT RCS 1 +

RDAC
RCORE
Note that the SC1406G regulates to the + side of R23; as a result, the minimum load dependent drop is Iout x R23. In addition, the ripple voltage across R23 provides a minimum input to the hysteretic comparator, so the SC1406G works well with very low ESR capacitors. The constant-current type of over current protection is provided via R23, RCLOH (R3), and RCLSET (R2). Current limiting will cycle from ICLMAX to ICLMIN until the load becomes less than ICLMAX: 10) ICLMIN := 2 VREF
RCLOH RCLSET RCS RCLOH RCLSET RCS
Without IMVP, the ROH (R6) and RHYS (R1) resistors set the hysteresis voltage via the following equation: 6) VHYS := 2 V REF
ROH RHYS
11) ICLMAX := 3 V REF
The factor of 2 is due to the fact that half of the total hysteresis occurs above the DC set point, half below, per Figure 1. Because output ripple is fed back to CMPREF via the R5/R21 divider, the uncorrected output ripple is increased. We correct for this later when selecting R1. The no load offset in a non-IMVP converter is set by R6 and R22. The zero load voltage is:
7) V := V NL DAC 1 +
ROH
ROFFSET
As in the case of the hysteresis resistor, IMVP requires an adjustment of the offset resistor value because at zero current, the current drawn by the offset resistor divider is mirrored into the R5/R21 divider, and increases the offset just as it increases the ripple. R22 is calculated by solving equation 4) for IOUT = 0A.
Design Example SC1406G: We can use the above equations to design a mobile voltage regulator circuit to meet the requirements of the Intel(R) 650/ 500MHz SpeedStep processor using values from the processor datasheet. This example is for reference only; your requirements, parts availability, and newer processors may require different component values. Contact Intel for the latest processor requirements. Note that in the calculations, results have been rounded to the nearest commonly available component value.
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Requirements: The critical processor requirements are: 1. VCC650MAXDC = 1.65V 2. VCC650MINDC = 1.485V 3. VCC650MAXTRANS = 1.715V 4. VCC650MINTRANS = 1.485V 5. VCC500MAXDC = 1.45V 6. VCC500MINDC = 1.25V 7. VCC500MAXTRANS = 1.45V 8. VCC500MINTRANS = 1.25V 9. ICC650MAX = 13.6A 10. ICC650SG = 2.2A 11. ICC500MAX = 9.5A 12. ICC500SG = 1.7A 13. dICC/dt = 1400A/mS (at the processor. Local decoupling reduces the requirement at the regulator.) The system requirements are to minimize the number of capacitors, and: 1. 2. VADAPTERMAX = 21V VBATTMIN = 10V
Figure 3 - Hysteretic Converter Response to a Positive Transient In a hysteretic converter with adaptive voltage positioning, like the SC1406, two conditions determine if you meet the positive transient requirements: D. VIMVP ( ICC650MAX - ICC650SG ) ESR E. VIMVP deltaV ( COUT) The first condition is easy to see if the ESR is too high, the transient response will fail. In the second condition, because the hysteretic converter responds in < 100ns, the capacitor does not droop very far before the inductor current starts ramping up. (This is not true of control schemes where time constants in the error amplifier cause delays.) Once the inductor current starts to rise, the increasing DV of the capacitor is offset by reduced DV from the ESR, so DV is constant. If the DV due to the charge taken from the capacitor before the inductor current reaches the load current (see the shaded area above) is less than VIMVP, then the transient response will pass. The maximum ESR requirement is: F. ESRMAX:=
Basic Calculations: The 0.85% DAC output voltage accuracy accounts for an uncertainty of 14mV at the 1.60V setting. In addition, 20mV of resistive drop is expected in the power distribution from the current sense resistor to the processor. A footnote in the processor specification reads that the long-term voltage should never exceed 1.65V. As a result, the nominal value of the noload voltage [V (0)] should be set accordingly. A. V NL := VCC650MAXDC - V TOL NL = 1.636 V V The full-load voltage (V (fl)) is set similarly, including tolerance and DC drop. B. V FL := VCC650MINDC + VTOL + VDIST VFL = 1.519 V The regulator is to be designed with 40mV of output ripple, so the effective IMVP voltage drop (VIMVP) is: C. VIMVP := V NL - VFL -
VRIPPLE 2 VIMVP = 0.098 V
(ICC650MAX - ICC650SG )
-3
VIMVP
Output Inductor and Capacitor Selection:
(
)
ESRMAX = 8.579 x 10
Output capacitance and ESR values are a function of transient requirements and output inductor value. The following figure illustrates the response of a hysteretic converter to a positive transient:
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For the second condition, we need to know the inductor value, which is a function of the highest desired switching frequency. The maximum frequency occurs at the highest input voltage. As a reasonable compromise between efficiency and component size, a maximum switching frequency of 300kHz is desired.
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Rearranging equation 1), we select the minimum inductor value. G. LMIN := dMIN through 28) are two differential pairs connected to the current sense resistor. In order to cancel out common-mode noise, resistor pairs R3-R4 and R5-R6 should be equal. For the time being, assume R3=R4=R5=R6=1kW. These values may be adjusted later if required. The current limit is a function of peak current and should be set at about 125% of the peak to allow for some overshoot of inductor current during transients. For L=1.5uH, and F=300kHz: ( VINMAX - VDAC) dMIN K. IPEAK := ICC650MAX + 2 LMIN FS IPEAK = 15.327 A So, set the current limit at approximately 18.5A. Using equation 10): L.
ICLMAX := IPEAK 1.25 ICLMAX = 19.159A
3 VREF RCLOH RCS ICLMAX
4
( VINMAX - VDAC) (ESRMAX + RCS)
FS VRIPPLE
-6
LMIN = 1.426 x 10
H
This value of inductance is required up to maximum load. Inductors with a swinging choke characteristic, where the zero current value of inductance is much less than the full load current inductance can be used, as long as the above restriction is met. A value of 1.5uH is used to allow tolerances. Then, the worst-case (low input voltage) response time (the time for the current to reach the new transient value) is: H.
dT := LMIN ICC650MAX - ICC650SG VINMIN - VDAC
-6
(
)
dT = 1.936 x 10
s
Add ~100ns for the SC1405/06 response. Since the shaded area is triangular, the total charge taken out of the capacitor = (DI ? Dt) / 2. Q = C ? DV = (DI ? Dt) / 2, therefore; I. CMINP :=
C
M. RCLSET :=
(ICC650MAX - ICC650SG ) ( dT + 100 10- 9 sec )
-4
RCLSET = 8.873 x 10
Using equation 6) we calculate RDAC: N. RDAC :=
2 VIMVP F
( VIMVP - ICC650MAX RCS) RCORE
ICC650MAX RCS
3
= 1.186 x 10
This condition applies only to the positive transient. For negative load steps, the capacitance also has to be large enough to absorb the energy in the inductance. Since:
2 2 I CC650MAX - ICC650SG J. CMINN := LMIN 2 2 V CC650MAXTRANS - VFL
RDAC = 1.397 x 10
The offset resistor, R22, is calculated from equation 8):
ROH + VNL RDAC VDAC
O.
ROFF :=
CMINN = 4.045 x 10
-4
F
VNL -1 VDAC
5
Using Panasonic SP-Caps, the EEFUE0E221R is 220uF at 2.5V with 15mW ESR. Two are sufficient to meet ESR requirements, but three are required to meet the capacitance requirement, when tolerances are considered. The Sanyo POSCAP 4TPC150 is a 150uF capacitor with a maximum ESR specification of 45mW; six are required to meet the ESR requirement. The resulting 900mF exceeds the capacitance requirement. Other Component Selection: As a compromise between current sensing accuracy, efficiency, and availability, a current sense resistor of 3mW is used. The power dissipation is I2xR, or 555mW, so choose a 1W or larger resistor for design margin. The connections to CMP, CMPREF, CL, and CLREF (pins 25
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ROFF = 1.068 x 10
Equation 5) is used to calculate R1 by calculating a new value of VHYS which accounts for the IMVP and offset dividers, and then plugging the resulting value into equation 3). P.
( ) (ROFF + ROH) ESR + RCS RCORE RCORE ROFF - RDAC ROH 2 ESR RCORE (ROFF + ROH)
VHYS := VRIPPLE RCORE ROFF - ROH RDAC
V
HYS
= 0.027 V
VREF ROH V HYS
5
Q. RHYS := 2
R HYS = 1.281 x 10
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The 55nS maximum delay from CO to the turn-off of the highside driver will result in somewhat larger than calculated ripple, especially at high line, high ESR, and low inductor values. For the example, the increase in output ripple is about 6mV. R1 can be adjusted for this, if desired. Once the design is complete, rerun the calculations for 1.35V to be sure the low voltage requirements are being met. Several small capacitors are required for signal filtering. Use SMT ceramic capacitors with an X7R or better temperature coefficient. C0G is preferred. C6 and C7, which filter the output voltage feedback, are sized to provide filtering beyond the fifth harmonic of the fundamental. The R5/R6 and C5/C6 components are balanced differential pairs that effectively filter both common-mode and differential noise sources that are troublesome in any high-performance switching converter: R. C6MAX:=
1 2 RCORE FS 5
- 10
ments sized for the required currents: 2.5A peak @ 1.5V, and 150mA peak @ 2.5V. PNP regulators are somewhat harder to stabilize than NPN regulators. They require low source impedance, with input decoupling <0.5 inches from the emitter of the pass element; one capacitor suffices if the pass elements are close enough together. The size of capacitor required varies according to the impedance back to the 3.3V source. If the bulk decoupling is within two inches, and the 3.3V is distributed using a trace of at least 1 inch in width, then a 22mF capacitor is sufficient. Otherwise, use at least 100mF. PNP regulators generally require some ESR in the output capacitors for stability purposes, but excess ESR can also create problems. The allowable range of output capacitor and ESR values, based on simulation and testing is shown in Figure 4 for the 1.5V output and Figure 5 for the 2.5V output.
$WAPA8hhpvATryrpv
!@# '@#
C6MAX = 1.061 x 10
F
Occasionally, due to layout-dependent noise on the CMP pin, the value of C6 and C7 must be increased. If multiple high frequency pulses are seen on the CO pin (pin 23), then additional capacitance is required. An additional capacitor is tied from the CO pin to the CMPREF pin to provide AC hysteresis during switching, and also helps to eliminate multiple pulses. Use a 1pF NPO capacitor for this purpose. C5 is sized similarly, using R3 and R4. Since the current-limit comparator does not affect the normal operation of the converter, the frequency requirement is only to the second harmonic, so as not to attenuate the fundamental. S. C5MAX:=
2 RCORE + RBAL FS 2
- 10
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#@$ !@$ @ !
%@#
ThiyrASrtv
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$
%
@TSAPu
Figure 4 - Recommended output C and ESR values (1.5V output)
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@% A A r p @ % h v ( @ & p h ' @ & h 8
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Ti h yrAS t r v
C5MAX = 1.326 x 10
F
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The DAC output requires a similar 1nF, X7R or C0G capacitor (C9) for high frequency noise filtering. Powering the SC1406: Vcc to the SC1406 can be either 5V, or 3.3V +/- 10%. 3.3V is recommended for lower power consumption, and because the UVLO function of the SC1406G provides protection for LDO outputs. Filter Vcc with an RC network; R18 should be 10W, C8, 0.1uF or greater. Linear Regulator Design: The SC1406G includes two linear regulator controllers, preset to 1.5V (VI/O) and 2.5V (VCLK), and sized to drive PNP pass elea 2000 Semtech Corp.
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Figure 5 - Recommended output C and ESR values (2.5V output) Pass Elements: The last thing to consider is the pass elements themselves. The drivers are sized to provide peak output current with a minimum beta of 50. The MMBT4403 is one choice for the 2.5V pass element, and the MJD45H11 for the 1.5V output, although there are many acceptable choices. Do not use a Darlington transistor; the high gain and extra poles create stability problems, and defeat the beta current limiting scheme.
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Soft-Start Design: The three outputs have two soft-start controls, with the two linear regulators sharing one of them. The soft-start timing is controlled with a capacitor charged by a nominal 1mA current source. The soft-start period is the time to charge the soft-start capacitors to Vref (though the voltage eventually terminates near Vcc). The soft-start capacitor value is calculated for a 2ms nominal time by: ICSS tSS -9 T. CSS := CSS = 1.176 x 10 F VREF The soft-start period for VCORE should be somewhat longer due to the higher power and larger amount of output capacitance to charge. Choosing 3ms results in C10=1800pF. Low Battery Design: The SC1406G provides a low-battery indication with a hysteresis current feature. That is, when the voltage at the LBIN pin is above the reference, the input bias current is very low. Once the threshold (a 1.225V bandgap) is reached and LBIN trips, a 0.6mA to 10mA current source must be overcome by the battery and divider before the converter is allowed to come on again. For the sample converter, assume VTRIP = 9.5V. Ignoring bias currents, and assuming R8=20kW. U.
R8 In the example schematic, R9 = 43kW to accommodate operation down to 4.5VDC. The rounded value gives a VTRIPLO of 9.62V. In order for LBIN to reset, the current source must be overpowered, so: VLBTRIP := VLBREF R8 + R9
VCIN (pin 4) must be referenced to the VIO rail; VCOUT (pin 3) can be tied to either VCLK or VCC , depending on the connection of the pull-up resistor. The clamp circuit has a dedicated reference, VCBYP (pin 5) that requires a 1.5nF capacitor for proper operation. The clamp circuit is not normally used in Pentium III mobile computers. To disable this function, tie VCIN to analog ground, with VCOUT and VCBYP open. Other Features and Functions: ENABLE is a 5V-safe CMOS input with an upper threshold voltage at 70% of Vcc and a lower threshold of 0.8V. It can be used in two different ways. One is to tie ENABLE to the PWRDY pin of the SC1405; this will bring both the SC1405 and SC1406 up properly even if ENABLE can be active before the system 5V supply is stable. Alternately, the ENABLE lines of both devices can be tied together. CO is the clock output from the SC1406 to the SC1405. POWERGOOD is LO (inactive) whenever any of the following conditions is present: 1 2 3 4 Vcore is more than 10% higher or lower than its setpoint, Either soft-start pin is lower than its threshold Vcc is below the UVLO threshold LBIN is active
POWERGOOD is HI (active) when none of the above is true, as during normal operating conditions. SC1405 Design Example: The main function of SC1405 is to rapidly drive the power MOSFETs on and off on using a break before make algorithm to prevent cross conduction in the FETs. FET selection:
V. V TRIPHIMAX:= VLBREF + R9 10 A +
VTRIPHIMAX = 10.986 V
V LBREF R8
W. V TRIPHIMIN := V LBREF + R9 6 A +
VTRIPHIMIN = 10.438 V

V LBREF R8
The hysteresis current, in this case provides a voltage hysteresis of 0.82V to 1.38V. C10 provides noise filtering at the LBIN input. The 1nF value is intended to provide attenuation at the lowest frequency load of the battery. To disable this feature, tie LBIN (pin 17) to Vcc of the SC1406 through a resistor (10kW is a good nominal value). Clamp Design: The clamp circuit is an open-collector uni-directional level shifter capable of driving a 16mA load with a 5ns typical delay time.
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The duty cycle (d) of the converter is a function of the input voltage. In most applications, where the converter runs directly from the battery, AC adapter, or even a regulated +5V source, d is always going to be much less than 50%. The low-side (or synchronous) FET, therefore, is conducting most of the time; further, because the diode clamps the voltage across the lowside FET, it switches with virtually zero voltage across it. The high-side (or control) FET conducts for a relatively small amount of time, but has to switch the entire voltage. Therefore, the control FET can have a relatively high RDS (ON), but needs to have low capacitive losses, and the synchronous FET needs to have a low RDS (ON), and can have higher capacitance. To accomplish this, one can use a single FET type, with two or more in parallel in the low-side, or one can use FET sets with individually optimized devices.
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The current in the control FET is approximately: X. IQ3RMS := ICC650MAX dMAX
IQ3RMS = 5.44 A
This current also should be used to size input capacitors; the three input capacitors need a ripple current rating of 1.8A each, to meet this requirement. The synchronous FET should be sized for the full output current. Since the drive is derived from 5V, both FETs should be sized using RDS(ON) and current ratings for Vgs=4.5V. Gate resistors are always recommended, and are required for the control FET and for multiple synchronous FETs (one resistor per gate). The value is dependent on FET selection and layout. Generally, start with 2.2W to 4.7W for R11 -13 to evaluate the circuit for EMI performance and Miller (gate to drain) capacitance effects. Increasing the high-side FET gate resistor value will lessen both problems, but at the expense of higher switching losses. Miller capacitance in the low-side FET can cause it to turn ON as the high-side FET turns on. It acts as a charge-pump capacitor to couple the current from the fast dV/dt on the drain into the gate. The voltage that appears on the low-side FET gate is:
CDS dV CGS dT If the voltage is sufficient to conduct significant current, then efficiency is poor, and in extreme cases, the devices can be damaged. For a given FET, Cgs is fixed, so one possible solution is to slow down dV/dt; another is to reduce Zdrive. Reducing Zdrive is primarily a function of layout and FET selection, since the internal Rg of the FET can be on the order of 10W. The SC1405 driver is typically 1W; so, given the short (10-20ns) dt, Zdrive can be dominated by trace inductance. For long gate drive traces, this inductance can resonate with the gate capacitance; in this case, a few ohms of gate resistance can damp the circuit and actually reduce the peak gate voltage. However, the best practice is to locate the SC1405 as near as possible to the low-side FET and run wide traces to the gate.
The charge pump capacitor needs to be low impedance, with a value at least 100 times the gate capacitance it has to charge. Ceramic capacitors are recommended. Schottky diodes are recommended for D1. Wide traces are also required for the charge pump traces. In very low power situations, the low side drive may be disabled via use of the SMOD pin (pin 5). This pin effectively prevents reverse current from flowing in the inductor, so the inductor current becomes discontinuous and the operating frequency is reduced. The reduced losses related to circulating current and faster switching need to be compared with the additional loss in using the diode rather than the synchronous rectifier to determine whether it improves low load efficiency in the system application. In addition, the system must supply the SMOD signal at the appropriate time. Phase Node Design: The phase node is one of the most critical nodes in the converter design, and must be treated with care. When neither Q3 nor Q4 is on, the inductor current flows through D2. D2 should be a Schottky diode with a forward voltage at the peak inductor current less than the forward voltage of the parasitic diode of the FET, to keep it from conducting, and improving efficiency. Holding the gate of Q4 low until the phase node reaches 1V for a high to low transition provides shoot-through protection. For a low to high transition, the high-side driver is held off by an internal 20ns delay. This period may be extended using C15, connected to pin 6, to provide an additional delay of approximately 1ns/pF. Size C15 to provide dead time for the worstcase drive conditions given the choice of control FET and gate drive resistor. The phase node voltage at DRN (pin 12) must not go below -2V; very short (<25nS) pulses to -5V can be tolerated. Excessive negative transients may result in double pulsing of the gate drive, and in severe cases, device damage. The phase node, since it switches at very high rates of speed, is generally the largest source of common-mode noise in the converter circuit. For this reason, it should be kept to a minimum size consistent with its connectivity and current carrying requirements. Occasionally, a snubber network (R17/ C18) is required to dampen parasitic ringing on the phase node caused by parasitic inductance and capacitance excited by the switching. One approach to snubber design is to record the frequency and amplitude of ringing before the snubber, then add pure capacitance until the frequency is reduced, then adding resistance until the required damping is achieved.
Y.
VG := ZDRIVE
Other potential solutions are to choose FETs with a low Cds/Cgs ratio, low Rg, or add a capacitor from the low-side gate drive to ground to externally lower the Cds/Cgs ratio. Charge Pump Design: The high-side drive circuit is tied to the source of the FET at DRN (pin 12) and rides along the switching (phase) node rather than being hard referenced to ground. The drive circuit makes use of this switching action to pump charge from the 5V source up to the BST pin (pin 14) to drive the control FET. When Q4 and Q5 are ON, C17 is charged through D1 to nearly 5V; when Q4 and Q5 turn off, this voltage is available to turn Q3 on. C17 rides along with the source, maintaining the drive level.
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Additional Functions: The SC1405 also provides two voltage protection functions: 1 2 A drive voltage under voltage lockout (UVLO) with output on PRDY, pin 7 An output over voltage protection (OVP) using input OVPS, pin 1 In addition: 1. Separate the noisy and quiet areas of the circuit. A significant benefit of the controller/driver architecture is that the control circuit does not have to coexist in an environment of thousands of volts and amps per microsecond. Place the SC1405 so as to reduce the trace length to the synchronous rectifier(s). Place the current-sense resistor as close as possible to the output capacitors; inductance from the voltage sense point to ground results in extra output ripple. Connections and routing of the differential pairs are critical. The first three items are essential; the others are suggested for additional guidance. a. Run the traces as close together as possible. b. Use minimum width traces to reduce capacitive coupling. c. Run a single pair as far as possible; split them at the resistors as close as possible to the SC1406; put the filter capacitors as close as possible to the device. d. In noisy environments, use a guard ring (ground trace around the differential pair). Tie the ring to ground every 2-4 cm. e. Run the traces in a quiet layer; use the minimum number of vias. Minimize the area of the switching node and any other high-speed nodes. Layout the protection circuitry (OVP, LBIN) keeping noise in mind: a. Minimize the length and area of traces to the pins. b. Put the noise filter capacitor next to the pin.
UVLO shuts off the drivers when Vcc is less than 4.4Vdc; in this condition, PRDY is driven low, and may be used to disable the SC1406G as well. OVP is implemented using a resistive divider to a 1.20V +/- 55mV reference. In order to keep the voltage within the 2.1V processor specification: Z. VREFMAX:= V OVPMAX
R14 R14 + R15
2. 3.
4.
With R14=10kW, R15=6.65kW. Solving this equation for the minimum trip voltage yields VOVPMIN=1.906V. Since this is only ~250mV from the zero load voltage, a noise filter capacitor (C14) is required, and should be chosen that the R14||C15 time constant is longer than the minimum switching period. The OVP input has very fast response, so C14 needs to be located directly at the pin, and the length of the OVP trace should be minimized.. Ground pin 1 to disable OVP. A logic output signal DPSPDR (pin11) mirrors BG when SMOD is HI; it is HI when SMOD is LO. Additional notes: Since the SC1405 puts out large, sharp pulses, decoupling and grounding are very important. The Vcc decoupling capacitor, C16 should be at least 1uF ceramic, and located right at the chip with the + terminal connected directly to Vcc (pin 8) and the terminal connected directly to PGND (pin 10). Note that the SC1405 connects to both the power and analog grounds. Grounding is described in the following section. LAYOUT GUIDELINES: As with any high-speed switching converter, the area of high current loops needs to be minimized. The two major loops are (referring to Figure 2): 1. 2. From the input capacitors, through Q3, L1, and C19 C24, returning through PGND; From Q4/Q5 through L1 and C19 C24, returning through PGND.
5. 6.
Secondary loops are in the gate drive circuitry: 1. 2. From C17 through the SC1405, R13 and Q3, returning through the phase node. From C16 through the SC1405, R11/R12 and Q4/Q5, returning through PGND.
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SC1406G
POWER MANAGEMENT Sample Layout
The following shows the layout of the SpeedStep VRM. Additional data, including electronic format schematic and layout files, as well as experienced layout assistance is available from your local Semtech field applications engineer.
Figure 9 - PowerStep VRM - Inner Layer
Figure 6 - PowerStep VRM Top Layer
Figure 10 - PowerStep VRM - Top Silkscreen
Figure 7 - PowerStep VRM - Bottom Layer
Figure 11 - PowerStep VRM - Bottom Silkscreen
Figure 8 - PowerStep VRM - Ground Layer
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SC1406G
POWER MANAGEMENT Bill of Materials
Critical Component Recommendations: A list of components used successfully in this and/or similar circuits appears below. Listing does not necessarily indicate available supply. Table 2 - Critical Components Supplies
Comp onent Outp ut Ind uctor Outp ut Cap acitors Manufacturers Panasonic Sumid a Kernet Panasonic Sanyo International Rectifier V ish ay/Siliconis IR C Panasonic V ish ay/Dale Series or Par t N umb er Series PCC-N 6, PCC-S1 Series CDEP134 (H) KO Cap , Series T520 SP Cap , Series CB POSCA P, Series TPx IRF7809A , IRF7811A Si4874, Si4884 Series LRF3W, LRF2010 Series ERJM-1WST Series WSL, WSR
Pow er MOSFETS Current Sense Resistor
Table 3 - Critical Supplier Contacts
COMPAN Y International Rectifier IR C Kernet Panasonic Sanyo Sumida TDK Vishay/Dale Vishay/Siliconix CON TACT Web : http ://w w w.ir f.com/p roduct-info/ Phone: (310) 726-8000 Web : http ://w w w.irctt.com/ Phone: (888) 472-4376 Web : http ://w w w.kernet.com/ Phone: (864) 963-6300 Web : http ://w w w.p anasonic.com/p ic/ecg/ Phone: (201) 348-7522 Web : http ://w w w.sanyovideo.com/ Phone: (619) 661-6835 Web : http ://w w w.sumida.com/ Phone: (847) 956-0666 Web : http ://w w w.comp onent.tdk.com/comp onents/comp onents.html Phone: (847) 390-4373 Web : http ://w w w.vishay.com/b rands/dale Phone: (402) 564-3131 Web : http ://w w w.vishay.com/b rands/siliconix/ Phone: (800) 554-5565
CONCLUSION: The SC1405/06G PowerStep chip set provides a complete, optimized solution for the power requirements of Intels SpeedStep processors. Evaluation kits and application notes are available. For further information, please see the Semtech website (www.semtech.com), or contact your local Semtech field applications engineer.
a 2000 Semtech Corp.
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SC1406G
POWER MANAGEMENT
Figure 12 - SpeedStep Transition, 1.60V to 1.35V
Figure 13 - SpeedStep Transition, 1.35V to 1.60V
Figure 14 - 0A to 12A Transient Load Response
Figure 15 - 12A to 0A Transient Load Response
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SC1406G
POWER MANAGEMENT
Output Ripple Voltage @ VIN = 6.0V
Figure 16 - VOUT = 1.6V, IOUT = 2.0A
Figure 17 - VOUT = 1.6V, IOUT = 12.0A
Output Ripple Voltage @ VIN = 18V
Figure 18 - VOUT = 1.6V, IOUT = 2.0A
Figure 19 - VOUT = 1.6V, IOUT = 12.0A
a 2000 Semtech Corp.
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SC1406G
POWER MANAGEMENT
Load Regulation & Efficiency
E fficiencyvs. V out 89.50%
1 . 600
Line Regulation & Efficiency
Vout = 1 . 60V Vout = 1 . 35V
89.00%
1 . 550
88.50%
1 . 500
88.00%
1 . 450
87.50%
1 . 400
87.00%
1 . 350
86.50% 1.100
1 . 300
1.300
1.500 VV out,
1.700
1.900
5. 000
7. 000
9. 000
1 1 . 000
1 3. 000
1 5. 000
1 7. 000
1 9. 000
21 . 000
23. 000
V i n, V
Figure 20 - VIN = 12V, VO = 1.6V
Figure 21 - VOUT = 1.6V, IOUT = 8.0A
Efficiency vs Output Voltage
E f f i ci ency vs . Vout 89. 50%
Efficiency vs Input Voltage
Vout=1 . 35V 90. 00% Vout=1 . 6V
89. 00%
89. 00%
88. 50%
88. 00%
88. 00%
87. 00%
87. 50%
86. 00%
87. 00%
85. 00%
86. 50% 1 . 1 00 1 . 300 1 . 500 V out , V 1 . 700 1 . 900
84. 00% 4. 000 6. 000 8. 000 1 0. 000 1 2. 000 1 4. 000 1 6. 000 1 8. 000 20. 000 22. 000
V i n, V
Figure 22 - VIN = 12V, IOUT = 8.0A
Figure 23 - VOUT = 1.3V, IOUT = 8.0A
a 2000 Semtech Corp.
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SC1406G
POWER MANAGEMENT
Supply Current vs VIN, Temperature @ UVLO mode
400
Supply Current vs VIN. Temperature @ Operating mode
8 7
350 6 300 100'C 20'C 0'C Current, mA Current, uA 5 4 3 200 2 150 3 4 Voltage, V 5 6 1 3 4 Voltage, V 5 6 Operating @100'C Operating @ 20'C Operating @ 0'C
250
Figure 24 DAC Output vs Temperature
1.8 1.6
Figure 25 Power Good Threshold vs Temperature
120
110
1.4 1.2 1.0 0.8 0.6 0 20 40 60 80 100 Temperature, 'C Vout @ 1.675V Vout @ 1.350V Vout @ 0.900V DAC, V
Volts
100
VhCore VLCore
90
80 0 20 40 60 80 100 Tem perature 'C
Figure 26 Hysteresis Setting Current vs Temperature
120 100 80 60 40 20 0 0 20 40 60 80 100 Temperature, 'C
Figure 27 Current Limit Threshold vs Temperature
300 250 200 150 100 50 0 0 20 40 60 80 100 Temperaure, 'C 42.5k +10mV 42.5k -10mV 20k +10mV 20k -10mV
Current, uA
17k(+10mV) 17k(-10mV) 170k(+10mV) 170k(-10mV)
Figure 28
Figure 29
Current, uA
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SC1406G
POWER MANAGEMENT
Core Soft-Start Current vs Temperature
2.5
LDOs Soft-Start Current vs Temperature
2.5
2
2
Current
Current
1.5 DisCharge, mA Charge, uA 1
1.5 DisCharge, mA Charge, uA 1
0.5
0.5
0 0 20 40 60 80 100 Temperature, 'C
0 0 20 40 60 80 100 Temperature, 'C
Figure 30 Low Battery Monitor Threshold vs Temperature
2.0
Figure 31 LDOs Drive Currents vs Temperature
80 70
1.5
60 Current, mA 50 40 30 20 10 1.5V 2.5V
Voltage, V
1.0
0.5
0.0 0 20 40 60 80 100 Temperature, 'C
0 0 20 40 60 80 100 Temperature 'C
Figure 32 I/O LDO Load Regulation-Normalized for 1A
101.0%
Figure 33 CLK LDO Load Regulation-Normalized for 100mA
103% 102%
100.5% Regulation, % Regulation, %
101% 100% 99% 98% 97% 96%
100.0%
99.5%
99.0% 0.0 0.5 1.0 Current, A 1.5 2.0
95% 0 50 100 Current, mA 150 200
Figure 34
Figure 35
a 2000 Semtech Corp.
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SC1406G
POWER MANAGEMENT Outline Drawing - TSSOP-28
Contact Information
Semtech Corporation Power Management Products Division 652 Mitchell Rd., Newbury Park, CA 91320 Phone: (805)498-2111 FAX (805)498-3804
ECN 00-1128
a 2000 Semtech Corp. 28 www.semtech.com

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